ReP USP - Resultado da busca

Artigo de periodico
Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications (2023)
Silva, V C P; Martino, João Antonio ; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, TEMPERATURA, NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS
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ABNT
SILVA, V C P et al. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, v. 208, p. 1-5, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108729. Acesso em: 17 maio 2024.
APA
Silva, V. C. P., Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2023). Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, 208, 1-5. doi:10.1016/j.sse.2023.108729
NLM
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2024 maio 17 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
Vancouver
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2024 maio 17 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
Artigo de periodico
Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C (2022)
Sousa, Julia Cristina Soares; Perina, Welder F; Rangel, Roberto; Simoen, Eddy ; Veloso, Anabela; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, TRANSISTORES
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ABNT
SOUSA, Julia Cristina Soares et al. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C. Solid State Electronics, v. 189, p. 1-9, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2022.108238. Acesso em: 17 maio 2024.
APA
Sousa, J. C. S., Perina, W. F., Rangel, R., Simoen, E., Veloso, A., Martino, J. A., & Agopian, P. G. D. (2022). Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C. Solid State Electronics, 189, 1-9. doi:10.1016/j.sse.2022.108238
NLM
Sousa JCS, Perina WF, Rangel R, Simoen E, Veloso A, Martino JA, Agopian PGD. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C [Internet]. Solid State Electronics. 2022 ;189 1-9.[citado 2024 maio 17 ] Available from: https://doi.org/10.1016/j.sse.2022.108238
Vancouver
Sousa JCS, Perina WF, Rangel R, Simoen E, Veloso A, Martino JA, Agopian PGD. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C [Internet]. Solid State Electronics. 2022 ;189 1-9.[citado 2024 maio 17 ] Available from: https://doi.org/10.1016/j.sse.2022.108238
Artigo de periodico
Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature (2022)
Silva, Vanessa Cristina Pereira da; Martino, João Antonio ; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, ALTA TEMPERATURA
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ABNT
SILVA, Vanessa Cristina Pereira da et al. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature. Solid State Electronics, v. 191, p. 1-8, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2022.108267. Acesso em: 17 maio 2024.
APA
Silva, V. C. P. da, Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2022). Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature. Solid State Electronics, 191, 1-8. doi:10.1016/j.sse.2022.108267
NLM
Silva VCP da, Martino JA, Simoen E, Veloso A, Agopian PGD. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature [Internet]. Solid State Electronics. 2022 ;191 1-8.[citado 2024 maio 17 ] Available from: https://doi.org/10.1016/j.sse.2022.108267
Vancouver
Silva VCP da, Martino JA, Simoen E, Veloso A, Agopian PGD. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature [Internet]. Solid State Electronics. 2022 ;191 1-8.[citado 2024 maio 17 ] Available from: https://doi.org/10.1016/j.sse.2022.108267
Artigo de periodico
Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time (2014)
Nissimoff, Albert; Martino, João Antonio ; Aoulaiche, Marc; Veloso, Anabela; Witters, Liesbeth J.; Simoen, Eddy ; Claeys, Cor
Source: IEEE Electron Device Letters. Unidade: EP
Subjects: TRANSISTORES, MODELOS MATEMÁTICOS, CAPACITORES
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ABNT
NISSIMOFF, Albert et al. Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time. IEEE Electron Device Letters, v. 35, n. 6, p. 639-641, 2014Tradução . . Disponível em: https://doi.org/10.1109/led.2014.2319094. Acesso em: 17 maio 2024.
APA
Nissimoff, A., Martino, J. A., Aoulaiche, M., Veloso, A., Witters, L. J., Simoen, E., & Claeys, C. (2014). Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time. IEEE Electron Device Letters, 35( 6), 639-641. doi:10.1109/led.2014.2319094
NLM
Nissimoff A, Martino JA, Aoulaiche M, Veloso A, Witters LJ, Simoen E, Claeys C. Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time [Internet]. IEEE Electron Device Letters. 2014 ; 35( 6): 639-641.[citado 2024 maio 17 ] Available from: https://doi.org/10.1109/led.2014.2319094
Vancouver
Nissimoff A, Martino JA, Aoulaiche M, Veloso A, Witters LJ, Simoen E, Claeys C. Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time [Internet]. IEEE Electron Device Letters. 2014 ; 35( 6): 639-641.[citado 2024 maio 17 ] Available from: https://doi.org/10.1109/led.2014.2319094
Artigo de periodico
Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation (2014)
Nicoletti, Talitha; Santos, Sara Dereste dos; Martino, João Antonio ; Aoulaiche, Marc; Veloso, Anabela; Claeys, Cor ; Simoen, Eddy ; Jurczak, Malgorzata
Source: Solid-State Electronics. Unidade: EP
Subjects: TEMPERATURA, MICROELETRÔNICA
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ABNT
NICOLETTI, Talitha et al. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation. Solid-State Electronics, v. 91, p. 53-58, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.09.012. Acesso em: 17 maio 2024.
APA
Nicoletti, T., Santos, S. D. dos, Martino, J. A., Aoulaiche, M., Veloso, A., Claeys, C., et al. (2014). Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation. Solid-State Electronics, 91, 53-58. doi:10.1016/j.sse.2013.09.012
NLM
Nicoletti T, Santos SD dos, Martino JA, Aoulaiche M, Veloso A, Claeys C, Simoen E, Jurczak M. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation [Internet]. Solid-State Electronics. 2014 ; 91 53-58.[citado 2024 maio 17 ] Available from: https://doi.org/10.1016/j.sse.2013.09.012
Vancouver
Nicoletti T, Santos SD dos, Martino JA, Aoulaiche M, Veloso A, Claeys C, Simoen E, Jurczak M. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation [Internet]. Solid-State Electronics. 2014 ; 91 53-58.[citado 2024 maio 17 ] Available from: https://doi.org/10.1016/j.sse.2013.09.012
Trabalho de evento
Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs (2013)
Martino, João Antonio ; Santos, Sara Dereste dos; Simoen, Eddy ; Strobe, V.; Cretu, B.; Routoure, J.-M.; Carin, R.; Aoulaiche, Marc; Veloso, Anabela; Claeys, Cor
Source: EUROSOI 2013. Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits. Unidade: EP
Assunto: MICROELETRÔNICA (CONGRESSOS)
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ABNT
MARTINO, João Antonio et al. Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs. 2013, Anais.. Paris: Institut Superieur d'Électronique, 2013. . Acesso em: 17 maio 2024.
APA
Martino, J. A., Santos, S. D. dos, Simoen, E., Strobe, V., Cretu, B., Routoure, J. -M., et al. (2013). Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs. In EUROSOI 2013. Paris: Institut Superieur d'Électronique.
NLM
Martino JA, Santos SD dos, Simoen E, Strobe V, Cretu B, Routoure J-M, Carin R, Aoulaiche M, Veloso A, Claeys C. Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs. EUROSOI 2013. 2013 ;[citado 2024 maio 17 ]
Vancouver
Martino JA, Santos SD dos, Simoen E, Strobe V, Cretu B, Routoure J-M, Carin R, Aoulaiche M, Veloso A, Claeys C. Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs. EUROSOI 2013. 2013 ;[citado 2024 maio 17 ]
Artigo de periodico
On the Variability of the Front-/Back-Channel LF Noise in UTBOX SOI nMOSFETs (2013)
Santos, Sara Dereste dos; Nicoletti, Talitha; Martino, João Antonio ; Aoulaiche, Marc; Veloso, Anabela; Jurczak, Malgorzata; Simoen, Eddy ; Claeys, Cor
Source: IEEE Transactions on Electron Devices. Unidade: EP
Subjects: SILÍCIO, FILMES FINOS, AVALIAÇÃO DE DESEMPENHO, TRANSISTORES
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ABNT
SANTOS, Sara Dereste dos et al. On the Variability of the Front-/Back-Channel LF Noise in UTBOX SOI nMOSFETs. IEEE Transactions on Electron Devices, v. 60, n. 1, p. 444-450, 2013Tradução . . Disponível em: https://doi.org/10.1109/ted.2012.2227749. Acesso em: 17 maio 2024.
APA
Santos, S. D. dos, Nicoletti, T., Martino, J. A., Aoulaiche, M., Veloso, A., Jurczak, M., et al. (2013). On the Variability of the Front-/Back-Channel LF Noise in UTBOX SOI nMOSFETs. IEEE Transactions on Electron Devices, 60( 1), 444-450. doi:10.1109/ted.2012.2227749
NLM
Santos SD dos, Nicoletti T, Martino JA, Aoulaiche M, Veloso A, Jurczak M, Simoen E, Claeys C. On the Variability of the Front-/Back-Channel LF Noise in UTBOX SOI nMOSFETs [Internet]. IEEE Transactions on Electron Devices. 2013 ; 60( 1): 444-450.[citado 2024 maio 17 ] Available from: https://doi.org/10.1109/ted.2012.2227749
Vancouver
Santos SD dos, Nicoletti T, Martino JA, Aoulaiche M, Veloso A, Jurczak M, Simoen E, Claeys C. On the Variability of the Front-/Back-Channel LF Noise in UTBOX SOI nMOSFETs [Internet]. IEEE Transactions on Electron Devices. 2013 ; 60( 1): 444-450.[citado 2024 maio 17 ] Available from: https://doi.org/10.1109/ted.2012.2227749

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